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ICSLV810
Buffer/Clock Driver
Description
The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout buffer. This device is specifically designed for data communications clock management. The large fanout from a single input line reduces loading on the input clock. The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal distribution.
Features
* Packaged in 20-pin QSOP/SSOP * Split 1:10 fanout Buffer * Maximum skew between outputs of different * * * * * * *
packages 0.75 ns Max propagation delay of 3.8 ns Operating voltage of 1.5 V to 2.5 V on Bank A Operating voltage of 1.5 V to 2.5 V on Banks B and C Advanced, low power, CMOS process Industrial temperature range -40 C to +85 C 3.3 V tolerant input when VDDA=2.5 V Available in Pb (lead) free packaging
Block Diagram
VDDA
CLK 1 CLK 2 CLK 3 CLK 4 CLKIN CLK 5 CLK 6 CLK 7 CLK 8 CLK 9 CLK 10
VDDB VDDC
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
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ICSLV810 Buffer/Clock Driver
Pin Assignment
CLKIN GND CLK 1 VDDA CLK 2 GND CLK 3 VDDA CLK 4 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDB CLK 10 CLK 9 GND CLK 8 VDDC CLK 7 GND CLK 6 CLK 5
20 pin (150mil) SSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
CLKIN GND CLK1 VDDA CLK2 GND CLK3 VDDA CLK4 GND CLK5 CLK6 GND CLK7 VDDC CLK8 GND CLK9 CLK10 VDDB
Pin Type
Input Power Output Power Output Power Output Power Output Power Output Output Power Output Power Output Power Output Output Power Clock input. Connect to ground. Clock output. Connect to +1.5 - +2.5 V. Clock output. Connect to ground. Clock output. Connect to +1.5 - +2.5 V. Clock output. Connect to ground. Clock output. Clock output. Connect to ground. Clock output. Connect to +1.5 - 2.5 V. Clock output. Connect to ground. Clock output. Clock output. Connect to +1.5 - 2.5 V.
Pin Description
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
Revision 101305 tel (408) 297-1201
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ICSLV810 Buffer/Clock Driver
External Components
The ICSLV810 requires a minimum number of external components for proper operation.
with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Decoupling Capacitors
Decoupling capacitors of 0.01F must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitors should be mounted on the component side of the board as close to the VDD pins as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output.
Series Termination Resistor
When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICSLV810. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD MAX All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDDA + 1.2 V -40 to +85C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured with respect to GND), VDDA Power Supply Voltage (measured with respect to GND), VDDB Power Supply Voltage (measured with respect to GND), VDDC
Min.
-40 1.425 1.425 1.425
Typ.
Max.
+85 2.625 2.625 2.625
Units
C V V V
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
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ICSLV810 Buffer/Clock Driver
DC Electrical Characteristics--CLKIN and Bank A
VDDA = 2.5 V, Ambient Temperature -40 C to +85 C
Parameter
Operating Voltage Quiescent Power Supply Current Short Circuit Current Input High Voltage, CLKIN Input Low Voltage, CLKIN Output High Voltage Output Low Voltage Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance
Symbol
VDDA IDDA IOS VIH VIL VOH VOL IIH IIL II CIN COUT
Conditions
No Load F = 40 MHz CLK 1 - 5 Guaranteed Logic Level High Guaranteed Logic Level Low VIN = VIH or VIL VIN = VIH or VIL VDD = max VDD = max VDD = max VIN = 0V, Note1 VOUT = 0V, Note1 IOH = -7 mA IOL =12 mA VIN = 2.4 V VIN = 0.5 V VIN = VDD (max)
Min.
1.425
Typ.
Max.
2.625
Units
V mA mA V
15 80 1.6
0.8 1.8 0.4 1 -1 20 5 5.5 6.0 8.0
V V V A A A pF pF
Note1: This parameter is not tested, guaranteed by design.
DC Electrical Characteristics--Bank B
VDDB = 2.5 V, Ambient Temperature -40 C to +85 C, unless otherwise noted
Parameter
Operating Voltage Quiescent Power Supply Current
Symbol
VDDB IDDB
Conditions
VDDB = 2.5 V No Load F = 40 MHz VDDB = 1.5 V No Load F = 40 MHz
Min.
1.425
Typ.
Max.
2.625
Units
V mA
7
3 CLK8-10 CLK8-10 35 80
mA mA mA
Short Circuit Current
IOS
VDDB = 1.5 V VDDB = 2.5 V
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
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ICSLV810 Buffer/Clock Driver
Parameter
Output High Voltage
Symbol
VOH
Conditions
VDDB = 1.5 V VIN = VIH or VIL VDDB = 2.5 V VIN = VIH or VIL IOH = -7 mA IOH = -7 mA IOL =12 mA IOL =12 mA
Min.
1.1 1.8
Typ.
Max.
Units
V V
Output Low Voltage
VOL
VDDB = 1.5 V VIN = VIH or VIL VDDB = 2.5 V VIN = VIH or VIL
0.42 0.4 1 -1 20 5 5.5 6.0 8.0
V V A A A pF pF
Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance
IIH IIL II CIN COUT
VDDB = max VDDB = max VDDB = max, VIN = VDD (max) VIN = 0V, Note1 VOUT = 0V, Note 1
Note1: This parameter is not tested, guaranteed by design.
DC Electrical Characteristics--Bank C
VDDC = 2.5 V, Ambient Temperature -40 C to +85 C, unless otherwise noted
Parameter
Operating Voltage Quiescent Power Supply Current
Symbol
VDDC IDDC
Conditions
VDDC = 2.5 V No Load F = 40 MHz VDDC = 1.5 V No Load F = 40 MHz
Min.
1.425
Typ.
Max.
2.625
Units
V mA
3
2 CLK6-7 CLK6-7 IOH = -7 mA IOH = -7 mA IOL =12 mA IOL =12 mA 1.1 1.8 0.42 0.4 1 -1 35 80
mA mA mA V V V V A A
Short Circuit Current Output High Voltage
IOS VOH
VDDC = 1.5 V VDDC = 2.5 V VDDC = 1.5 V VIN = VIH or VIL VDDC = 2.5 V VIN = VIH or VIL
Output Low Voltage
VOL
VDDC = 1.5 V VIN = VIH or VIL VDDC = 2.5 V VIN = VIH or VIL
Input High Current Input Low Current
IIH IIL
VDDC = max VDDC = max
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
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ICSLV810 Buffer/Clock Driver
Parameter
Input High Current Input Capacitance Output Capacitance
Symbol
II CIN COUT
Conditions
VDDC = max, VIN = VDD (max) VIN = 0V, Note1 VOUT = 0V, Note 1
Min.
Typ.
Max.
20
Units
A pF pF
5 5.5
6.0 8.0
Note1: This parameter is not tested, guaranteed by design.
AC Electrical Characteristics--Bank A
VDDA = 2.5 V, Ambient Temperature -40 C to +85 C
Parameter
Output Skew: skew between outputs of same package Pulse Skew: skew between opposite transitions of same output (tPLH-tPHL) Propagation Delay
Symbol
tSK(0)
Conditions
CL = 3 pF, RL = 500 Figure 3 CL = 3 pF, RL = 500 Figure 4 CL = 3 pF, RL = 500 Figure 2 CL = 3 pF, RL = 500 Figure 5 CL = 3 pF, RL = 500 CL = 3 pF, RL = 500 All Outputs CL = 3 pF, RL = 500
Min.
-200
Typ.
Max. Units
200 ps
tSK(P)
-200
200
ps
tpLH / tpHL
1.5
2.6
3.5
ns
Part to Part Skew
tSK(t)
-650
650
ps
Output Rise Time 20% to 80% Output Fall Time 80% to 20% Additive Jitter Duty Cycle Measured at VDD/2 Duty Cycle, VDDA=1.8V Output Frequency Range
tr(o) tf(o) tJ DC DC
0.8 0.8 50 45 40 1 50 55 60 133
ns ns ps % % MHz
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
Revision 101305 tel (408) 297-1201
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ICSLV810 Buffer/Clock Driver
AC Electrical Characteristics--Bank B
VDDB = 2.5 V, Ambient Temperature -40 C to +85 C, unless otherwise noted
Parameter
Output Skew: skew between outputs of same package Pulse Skew: skew between opposite transitions of same output (tPLH-tPHL) Propagation Delay
Symbol
tSK(0) tSK(P)
Conditions
CL = 3 pF, RL = 500 Figure 3 CL = 3 pF, RL = 500 Figure 4 CL = 3 pF, RL = 500, VDDB = 1.5 V Figure 2 CL = 3 pF, RL = 500, VDDB = 2.5 V Figure 2
Min.
-200 -200
Typ.
Max. Units
200 200 ps ps
tpLH / tpHL
5.5
ns
1.5
2.6
3.5
ns
Part to Part Skew
CL = 3 pF, RL = 500 VDDB = 1.5 V Figure 5 CL = 3 pF, RL = 500 VDDB = 2.5 V Figure 5
-1
1
ns
-650
650
ps
Output Rise Time 20% to 80%
tr(o)
CL = 3 pF, RL = 500 VDDB = 1.5 V CL = 3 pF, RL = 500 VDDB = 2.5 V
1.0 0.8 1.0 0.8 34 50 45 40 1 50 55 60 133
ns ns ns ns ps ps % % MHz
Output Fall Time 80% to 20%
tf(o)
CL = 3 pF, RL = 500 VDDB = 1.5 V CL = 3 pF, RL = 500 VDDB = 2.5 V
Additive Jitter
tJ
All Outputs, VDDB = 1.5 V All Outputs, VDDB = 2.5 V
Duty Cycle Measured at VDD/2 Duty Cycle, VDDB = 1.8V Output Frequency Range
DC DC
CL = 3 pF, RL = 500
MDS LV810 F Integrated Circuit Systems, Inc.
7
525 Race Street, San Jose, CA 95126
Revision 101305 tel (408) 297-1201
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ICSLV810 Buffer/Clock Driver
AC Electrical Characteristics--Bank C
VDDC = 2.5 V, Ambient Temperature -40 C to +85 C, unless otherwise noted
Parameter
Output Skew: skew between outputs of same package Pulse Skew: skew between opposite transitions of same output (tPLH-tPHL) Propagation Delay
Symbol
tSK(0) tSK(P)
Conditions
CL = 3 pF, RL = 500 Figure 3 CL = 3 pF, RL = 500 Figure 4 CL = 3 pF, RL = 500, VDDC = 1.5 V Figure 2 CL = 3 pF, RL = 500, VDDC = 2.5 V Figure 2
Min.
-200 -200
Typ.
Max. Units
200 200 ps ps
tpLH / tpHL
5.5
ns
1.5
2.6
3.5
ns
Part to Part Skew
CL = 3 pF, RL = 500 VDDC = 1.5 V Figure 5 CL = 3 pF, RL = 500 VDDC = 2.5 V Figure 5
-1
1
ns
-650
650
ps
Output Rise Time 20% to 80%
tr(o)
CL = 3 pF, RL = 500 VDDC = 1.5 V CL = 3 pF, RL = 500 VDDC = 2.5 V
1.0 0.8 1.0 0.8 34 50 45 40 1 50 55 60 133
ns ns ns ns ps ps % % MHz
Output Fall Time 80% to 20%
tf(o)
CL = 3 pF, RL = 500 VDDC = 1.5 V CL = 3 pF, RL = 500 VDDC = 2.5 V
Additive Jitter
tJ
All Outputs, VDDC = 1.5 V All Outputs, VDDC = 2.5 V
Duty Cycle Measured at VDD/2 Duty Cycle, VDDC=1.8V Output Frequency Range
DC DC
CL = 3 pF, RL = 500
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
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ICSLV810 Buffer/Clock Driver
Thermal Characteristics for 20QSOP
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
135 93 78 60
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Thermal Characteristics for 20SOIC
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
83 71 58 46
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
From O utput Under Test
CL=3pF 500 ohm
Figure 1. Load Circuit V IH Input tPLH tPHL V IL V OH Output Figure 2. Propagation Delay Input t PLH1 Output 1 tPHL1 VOH t SK tSK V OL VOH Output 2 tPLH2 tPHL2 ( t SK(O )=|t PLH2 -t PHL2 | or |t PLH1 -t PHL1 | ) Figure 3. Output Skew V OL Package 1 Output Package 2 Output V OL Output 1 Figure 4. Pulse Skew ( t SK(p)=|tpLH - tpH| ) Input t PLH1 t PHL1 V OH t SK t SK V OL V OH tPLH2 t PHL2 ( t SK(O)=|t PLH2 -t PHL2 | or |t PLH1 -t PHL1 | ) Figure 5. Part-to-Part Skew V OL Input t PLH1 t PHL1 V OH V OL
MDS LV810 F Integrated Circuit Systems, Inc.
9
525 Race Street, San Jose, CA 95126
Revision 101305 tel (408) 297-1201
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ICSLV810 Buffer/Clock Driver
Package Outline and Package Dimensions (20-pin QSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters Symbol Min Max
Inches* Min Max
E1 INDEX AREA
E
12 D
A A1 A2 b C D E E1 e L
1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0 8
.053 .069 .0040 .010 -.059 0.008 0.012 .007 .010 .337 .344 .228 .244 .150 .157 0.025 Basic .016 .050 0 8
*For reference only. Controlling dimensions in mm.
A 2 A 1 A
c
-Ce
b SEATING PLANE L
.10 (.004)
C
MDS LV810 F Integrated Circuit Systems, Inc.
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525 Race Street, San Jose, CA 95126
Revision 101305 tel (408) 297-1201
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ICSLV810 Buffer/Clock Driver
Package Outline and Package Dimensions (20-pin SSOP, 209 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters Symbol Min Max
Inches* Min Max
E1 INDEX AREA
E
12 D
A A1 A2 b c D E E1 e L
-- 2.00 0.05 -- 1.65 1.85 0.22 0.38 0.09 0.25 6.90 7.50 7.40 8.20 5.00 5.60 0.65 Basic 0.55 0.95 0 8
-- .079 .002 -- .065 .073 0.009 0.015 .0035 .010 .271 .295 .291 .323 .197 .220 0.0256 Basic .022 .037 0 8
*For reference only. Controlling dimensions in mm.
A 2 A 1 A
c
-Ce
b SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICSLV810RI ICSLV810RIT ICSLV810FI ICSLV810FIT ICSLV810RILF ICSLV810RILFT ICSLV810FILF ICSLV810FILFT
Marking
ICSLV810RI ICSLV810RI ICSLV810FI ICSLV810FI LV810RILF LV810RILF LV810FILF LV810FILF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
20-pin QSOP 20-pin QSOP 20-pin SSOP 20-pin SSOP 20-pin QSOP 20-pin QSOP 20-pin SSOP 20-pin SSOP
Temperature
-40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS LV810 F Integrated Circuit Systems, Inc.
11
525 Race Street, San Jose, CA 95126
Revision 101305 tel (408) 297-1201
www.icst.com
ICSLV810 Buffer/Clock Driver
Revision History
Rev.
A B
Originator
P.Griffith P.Griffith
Date
03/25/05 05/02/05
Description of Change
New device/datasheet. Released from Preliminary to final; changed Short Circuit Current parameter in 2.5 V DC Char table to 80 mA; changed Short Circuit Current parameter in 1.5 V DC Char table to 35 mA Added bullet in "Features" for operating voltage of 2.5 V on Bank A and specified that operating voltages of 1.5 and 2.5 V are on Banks B and C; changed block diagram input and pin 1 from IN to CLKIN; removed +1.5 V spec from pin 4 and pin 8 descriptions; added "VDDA + 1.2 V" to "All Inputs and Outputs" section of Absolute Maximum Ratings; added min and max values for Banks A, B, and C "Power Supply Voltage" in Recommended Operating Conditions; expanded DC Electrical Char tables in to include a separate table for Banks A, B, and C; expanded AC Electrical Char tables in to include a separate table for Banks A, B, and C; Added 209 mil 20-pin SSOP package and ordering info. Specified operating voltage on Bank A from 1.5V to 2.5V; Added figures 4 and 5 on page 10 to explain Pulse Skew and Part-to-Part Skew; Changed Output Frequency Max Specification to 133MHz in AC Electrical Char tables for Banks A, B, and C; Added Duty Cycle Spec for VDD = 1.5V in AC Electrical Char tables for Banks A, B, C; Changed CLK conditions in DC Electrical Char tables on Banks B and C; removed SOIC package. Added "LF" packaging and ordering info to both "R" and"F" packages.
C
P.Griffith
05/12/05
D E
P.Griffith K. Beckmeyer
06/21/05 07/27/05
F
K. Beckmeyer
10/13/05
MDS LV810 F Integrated Circuit Systems, Inc.
12
525 Race Street, San Jose, CA 95126
Revision 101305 tel (408) 297-1201
www.icst.com

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